Title: On-Chip Embedding Two Pattern Test for Large Sets of Vectors

In this paper, we propose a new on-chip embedding methodology for two pattern test for large sets of vectors. The initialization vector is shifted into the scan chain, and then the transition vector is generated by reseeding technique which modifies the current vector to the desired vector. Whenever the scan chain is fulfilled with the initialization vector, the reseeding logic is activated to generate the desired vector instead of only shifting the initialization vector one cycle. The transition (desired) vector is acquired in the next cycle. The advantages of our approach reduce not only the influence of embedded reseeding circuit but also the number of group seed by only reseeding the remaining patterns after the strategies of skew load and broad side are applied. Experimental results show that the number of group seed and thus test time are significantly improved, compared with previous work.